1. Field of the Disclosure
The present disclosure relates to memory design, and more particularly to generating a memory structural model that may be used for designing an efficient test and repair engine of a memory instance.
2. Description of the Related Art
Some processes for designing integrated circuits define memory devices as a set of parameterized templates. A chip designer may use such set of parameterized templates to design and incorporate certain memory devices into a design of an integrated circuit (IC). The parameterized templates are often provided by memory device design providers in the form of electronic files. The chip designer may conveniently incorporate instances of the memory devices into an IC by configuring parameters associated with the templates using various electronic design automation (EDA) tools.
The designing process of an IC includes a process of designing a test and repair engine for the memory instances. As part of this process, the test and repair engine may include generation of background data patterns that are written to the memory instance and then read back for comparison. By analyzing the programmed data patterns and the read data patterns, the test and repair engine may detect flaws in the operation of the memory instance and take remedial actions.
To design an efficient test and repair engine for a memory instance or design, a chip designer may use a logical model corresponding to the layout of the memory instance being incorporated into the IC design. However, the generation of the logical memory model may involve a large amount of time and computation. Further, the chip designer may not possess requisite information for generating the logical model. Hence, the process of designing the test and repair engine of a memory instance is often fraught with inefficiencies and difficulties.